FIG. 1 diagrammatically illustrates an encoded digital communication system comprised of a transmitter device 1, such as a first modem, that communicates with a receiving device 2, such a second modem, via a channel 4 therebetween. The input to the transmitter device 1 and the output of the receiving device 2 is digital data in the form of a serial stream of bits denoted as DATA OUT. The input data stream, DATA IN, is encoded such as by means of a trellis coded modulation scheme shown in FIG. 2. The output of the transmitter device 1 and the input of the receiver 2 are respective voltage levels, which ideally are the same. However, the channel can introduce both phase and amplitude distortion and both additive and multiplicative noise, to the transmitted signal.
In the trellis coded modulator of FIG. 2, an input serial bit stream denoted DATA IN is coupled to a serial-to-parallel converter 3, which converts the serial data stream into parallel form. One of the bit outputs 5 of the serial-to-parallel converter 3 is coupled to a rate ½ convolutional encoder 6, which produces two output bits u and y. These two bits plus the other bits (two in the illustrated example) from the serial-to-parallel converter 3 are coupled to a (one-out-of-sixteen) level mapper 7, which maps all of the possible combinations (sixteen in the present example) of the input bits (four in the example) into (sixteen) associated unique voltage levels at its output port denoted LEVEL OUT.
For non-limiting examples of U.S. Patents disclosing encoding and decoding schemes, including trellis-coded modulation (TCM) techniques, attention may be directed to the U.S. Patents to Gilbert et al, U.S. Pat. No. 5,737,365, and McCallister et al, U.S. Pat. No. 6,078,625.
In accordance with the encoding/decoding scheme described in the U.S. patent to Gilbert et al al, U.S. Pat. No. 5,737,365, multiple encoders are installed at a transmit site and multiple decoders are installed at a receiver site. In operation, one of a predetermined set of trellis codes is selected at a time—either by default or through a prior communication between the transmitting transceiver and the receiving transceiver. The receiver then determines the signal quality on the received trellises for that decoder. If the signal quality is too low for the selected set of trellises, the receiver will either request or select (depending upon whether the control lies in the transmitter or receiver) a set of trellises with greater immunity to noise. On the other hand, if the signal quality is relatively high, then trellises with an increased number of constellation points and higher data rates may be used. Namely, in Gilbert et al, code selection is based on the current signal and noise condition, and there is a corresponding encoder/decoder set for each of the predetermined trellis codes.
The U.S. Patent to McCallister et al, U.S. Pat. No. 6,078,625 discloses a decoding scheme that employs a concatenated decoder configured to match inner and outer codes, and resolve phase ambiguities without the need for differentially encoded user data.
Additional publications that describe encoding and decoding mechanisms include an article by G. Ungerboeck, entitled “Channel Coding With Multilevel/Phase Signals,” IEEE Transactions on Information Theory, January 1982, pp 55–67; an article by F. Q. Wang, entitled “Efficient Sequential Decoding of Trellis Codes,” Ph.D. Thesis, University of Notre Dame, December 1992, wherein the use of sequential decoding to decode TCM signals is described; and the text by S. Lin and D. J. Costello, entitled “Error Control Coding: Fundamentals and Application,” Prentice-Hall, 1983, which is a relatively complete description of sequential decoding and Viterbi decoding.
Sequential decoding is a well-known method of decoding digital data sequences which have been encoded using a convolutional encoder as in the communication system of FIG. 1. As such, it is a viable mechanism for single-loop high data rate digital subscriber loop (HDSL) communications. Now although a sequential decoder is a good trade-off between complexity and performance, it suffers from occasional ‘path loss’ or ‘loss of synchronization’ due to computational overload. In the present description, the term ‘loss of synchronization’ is synonymous with the term ‘path loss’.
The effect of path loss (or loss of synchronization) is that the sequential decoder must restart and then enter a path recovery mode of operation, during which it searches for the correct starting state or recovers synchronization before sequential decoding can resume. As long as the sequential decoder is in its normal decoding mode, its output is reliable and the probability of error is very low. However, during the period of time that the sequential decoder loses synchronization and is performing path recovery, its output is considerably less reliable and the probability of error is very high.
Therefore, it is desirable to minimize the time spent in performing path recovery, or recovering synchronization and, instead, to maximize the time spent performing sequential decoding. Accordingly, there is a need for a mechanism which will decrease the time spent in path recovery for a sequential decoder.